Study of ZrO(2) Gate Dielectric with Thin SiO(2) Interfacial Layer in 4H-SiC Trench MOS Capacitors.

The transition of SiC MOSFET structure from planar to trench-based architectures requires the optimization of gate dielectric layers to improve device performance. This study utilizes a range of characterization techniques to explore the interfacial properties of ZrO(2) and SiO(2)/ZrO(2) gate dielectric films, grown via atomic layer deposition (ALD) in SiC epitaxial trench structures to assess their performance and suitability for device applications. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements showed the deposition of smooth film morphologies with roughness below 1 nm for both ZrO(2) and SiO(2)/ZrO(2) gate dielectrics, while SE measurements revealed comparable physical thicknesses of 40.73 nm for ZrO(2) and 41.55 nm for SiO(2)/ZrO(2). X-ray photoelectron spectroscopy (XPS) shows that in SiO(2)/ZrO(2) thin films, the binding energies of Zr 3d(5/2) and Zr 3d(3/2) peaks shift upward compared to pure ZrO(2). Electrical characterization showed an enhancement of E(BR) (3.76 to 5.78 MV·cm(-1)) and a decrease of I(ON_EBR) (1.94 to 2.09 × 10(-3) A·cm(-2)) for the SiO(2)/ZrO(2) stacks. Conduction mechanism analysis identified suppressed Schottky emission in the stacked film. This indicates that the incorporation of a thin SiO(2) layer effectively mitigates the small bandgap offset, enhances the breakdown electric field, reduces leakage current, and improves device performance.